NAND-type flash memories can be divided into SLC (Single-Level Cell) NAND-type flash memories and MLC NAND-type flash memories according to the digits that can be stored in each memory cell.
Each memory cell of an SLC NAND-type flash chip may have two states: a high voltage state and a low voltage state, which represent the data 0 and 1, respectively. Such a memory cell may represent a data bit. A plurality of physical memory cells form a physical page, which may represent a same number of bits, namely a logic page.
Each memory cell of an MLC NAND-type flash chip may have four voltage states. MLC represents different data according to different voltage values. FIG. 1 is a schematic view illustrating voltage distribution of a memory cell of an MLC NAND-type flash chip, wherein MLC represents the data 11 when the voltage is between 0 and A, MLC represents the data 10 when the voltage is between A and B, MLC represents the data 01 when the voltage is between B and C, and MLC represents the data 00 when the voltage is between C and D. Such a memory cell may represent two data bits, and a physical page of an MLC NAND-type flash chip has bits 2 times the bits of a physical page of an SLC NAND-type flash chip.
Generally two logic pages of a same size as a physical page will be divided, wherein the low 0 or 1 forms an LSB (least significant bit), and the high 0 or 1 forms an MSB (most significant bit); that is to say, the two logic pages (the pages formed of the LSB and the MSB, respectively) share one physical page. In FIG. 1, the most significant bit (MSB) is on the left-most side of the binary data, and the least significant bit (LSB) is on the right-most side of the binary data.
Assuming the first voltage state (11) has an electron number of 0, the second voltage state (10) has an electron number of n, the third voltage state (00) has an electron number of 2n, and the fourth voltage state (01) has an electron number of 3n. Hereinafter the process of charging/discharging the read-write of a solid hard disk in the prior art is analyzed in detail by taking different orders as two examples.
1. Firstly, write data to a least significant bit (LSB), and then write data to a most significant bit (MSB); the data change relationship is shown in FIG. 2.
As data is first written to a least significant bit (LSB), the written data may be 1 or 0 and, accordingly, the data change relationship is as follows: 11 is changed into 11, or 11 is changed into 10. When 11 is changed into 11, a multi-layer memory cell does not need to be charged or discharged; when 11 is changed into 10, it needs to be charged with n electrons.
As data is then written to a most significant bit (MSB), the written data may be 1 or 0 and, accordingly, the data change relationship is as follows: 11 is changed into 11, or 11 is changed into 01, or 10 is changed into 10, or 10 is changed into 00. When 11 is changed into 11 or 10 is changed into 10, there is no real change, and it does not need to be charged or discharged; when 11 is changed into 01, it needs to be charged with 3n electrons; when 10 is changed into 00, it needs to be charged with n electrons.
2. Firstly, write data to a most significant bit (MSB), and then write data to a least significant bit (LSB); the data change relationship is shown in FIG. 3.
As data is first written to a most significant bit (MSB), the written data may be 1 or 0 and, accordingly, the data change relationship is as follows: 11 is changed into 11, or 11 is changed into 01. When 11 is changed into 11, it does not need to be charged or discharged; when 11 is changed into 01, it needs to be charged with 3n electrons.
As data is then written to a least significant bit (LSB), the written data may be 1 or 0 and, accordingly, the data change relationship is as follows: 11 is changed into 11, or 11 is changed into 10, or 01 is changed into 01, or 01 is changed into 00. When 11 is changed into 11 or 01 is changed into 01, there is no real change, and it does not need to be charged or discharged; when 11 is changed into 10, it needs to be charged with n electrons; when 01 is changed into 00, n electrons need to be discharged.
From the above analysis, when 1 is written to both the least significant bit (LSB) and the most significant bit (MSB) of the multi-layer memory cell, it does not need to be charged or discharged; when 0 is written to only one of the least significant bit (LSB) and the most significant bit (MSB) of the multi-layer memory cell, it needs to be charged once; when 0 is written to both the least significant bit (LSB) and the most significant bit (MSB) of the multi-layer memory cell and first written to the least significant bit (LSB), it needs to be charged twice; when 0 is written to both the least significant bit (LSB) and the most significant bit (MSB) of the multi-layer memory cell and first written to the most significant bit (MSB), it needs to be charged once and discharged once. In this way, since the LSB and MSB of an MLC-type flash chip share a physical memory cell, when the LSB or MSB is being programmed, the physical memory cell needs to be charged or discharged, and the times of frequent charging/discharging reduce the times of erasure of the MLC-type flash chip, resulting in abrasion of the flash chip and reducing the service life of the flash chip.
To sum up, the practical application of the existing charging/discharging control methods for MLC NAND-type flash chips is obviously inconvenient and deficient, thus it is necessary to make an improvement.